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User’s Manual U17894EJ9V0UD
10
4.5
Settings of Port Mode Register and Output Latch When Using Alternate
Function ..................................................................................................................................160
4.6
Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn)................................163
CHAPTER 5 EXTERNAL BUS INTERFACE .....................................................................................164
5.1
Functions of External Bus Interface ....................................................................................164
5.2
Registers Controlling External Bus Interface Functions ...................................................170
5.3
Setting Port Mode Register and Output Latch ....................................................................173
5.4
Number of Instruction Wait Clocks for Data Access..........................................................174
5.5
Number of Instruction Execution Clocks and Instruction Wait Clocks for Fetch
Access.....................................................................................................................................174
5.6
Number of Instruction Wait Clocks for External Wait Pin..................................................175
5.7
Timing of External Bus Interface Function..........................................................................176
5.7.1
Multiplexed bus mode...............................................................................................................177
5.7.2
Separate bus mode ..................................................................................................................181
5.8
Example of Connection to Memory ......................................................................................185
5.8.1
Connection of external logic (ASIC, etc.)..................................................................................185
5.8.2
Connection of synchronous memory ........................................................................................185
5.8.3
Connection of asynchronous memory ......................................................................................186
CHAPTER 6 CLOCK GENERATOR ...................................................................................................187
6.1
Functions of Clock Generator...............................................................................................187
6.2
Configuration of Clock Generator ........................................................................................188
6.3
Registers Controlling Clock Generator ...............................................................................190
6.4
System Clock Oscillator ........................................................................................................204
6.4.1
X1 oscillator ..............................................................................................................................204
6.4.2
XT1 oscillator............................................................................................................................204
6.4.3
Internal high-speed oscillator....................................................................................................207
6.4.4
Internal low-speed oscillator .....................................................................................................207
6.4.5
Prescaler ..................................................................................................................................207
6.5
Clock Generator Operation ...................................................................................................208
6.6
Controlling Clock ...................................................................................................................212
6.6.1
Example of controlling high-speed system clock ......................................................................212
6.6.2
Example of controlling internal high-speed oscillation clock .....................................................215
6.6.3
Example of controlling subsystem clock ...................................................................................217
6.6.4
Example of controlling internal low-speed oscillation clock ......................................................219
6.6.5
CPU clock status transition diagram.........................................................................................220
6.6.6
Condition before changing CPU clock and processing after changing CPU clock ...................225
6.6.7
Time required for switchover of CPU clock and main system clock .........................................227
6.6.8
Conditions before clock oscillation is stopped ..........................................................................228
CHAPTER 7 TIMER ARRAY UNIT.....................................................................................................229
7.1
Functions of Timer Array Unit ..............................................................................................229
7.1.1
Functions of each channel when it operates independently .....................................................229
7.1.2
Functions of each channel when it operates with another channel...........................................230
7.1.3
LIN-bus supporting function (channel 7 only) ...........................................................................230
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